1. Field of the Invention
The present invention relates to a magnetic random access memory (MRAM) which stores “1”- and “0”-data using a magnetoresistive effect.
2. Description of the Related Art
In recent years, many memories which store data by new principles have been proposed. One of them is a magnetic random access memory which stores “1”- and “0”-data using a tunneling magnetoresistive (to be referred to as TMR hereinafter) effect.
As a proposal for a magnetic random access memory, for example, Roy Scheuerlein et al, “A 10 ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in each Cell”, ISSCC2000 Technical Digest, p. 128 is known.
A magnetic random access memory stores “1”- and “0”-data using TMR elements. As the basic structure of a TMR element, an insulating layer (tunneling barrier) is sandwiched between two magnetic layers (ferromagnetic layers). However, various TMR element structures have been proposed to optimize the MR (MagnetoResistive) ratio.
Data stored in the TMR element is determined on the basis of whether the magnetizing states of the two magnetic layers are parallel or antiparallel. “Parallel” means that the two magnetic layers have the same magnetizing direction. “Antiparallel” means that the two magnetic layers have opposite magnetizing directions.
Normally, one (fixed layer) of the two magnetic layers has an antiferromagnetic layer. The antiferromagnetic layer serves as a member for fixing the magnetizing direction of the fixed layer. In fact, data (“1” or “0”) stored in the TMR element is determined by the magnetizing direction of the other (free layer) of the two magnetic layers.
When the magnetizing states in the TMR element are parallel, the resistance of the insulating layer (tunneling barrier) sandwiched between the two magnetic layers of the TMR element is minimized. For example, this state is defined as a “1”-state. When the magnetizing states in the TMR element are antiparallel, the resistance of the insulating layer (tunneling barrier) sandwiched between the two magnetic layers of the TMR element is maximized. For example, this state is defined as a “0”-state.
Currently, various kinds of cell array structures have been examined for a magnetic random access memory from the viewpoint of increasing the memory capacity or stabilizing write/read operation.
For example, currently, a magnetic random access memory in which one memory cell is formed from one select MOS transistor and one TMR element (or an MTJ (Magnetic Tunnel Junction) element), and 1-bit data is stored using two memory cells is known.
However, in this magnetic random access memory, it is difficult to increase the memory capacity. This is because this cell array structure requires two TMR elements and two select MOS transistors to store 1-bit data.
A cell array structure in which TMR elements connected to word lines and bit lines are arranged at the intersections of the word lines and the bit lines, i.e., a cross-point cell array structure is known.
According to the cross-point cell array structure, the memory cell size can be reduced because no select MOS transistors are used. As a consequence, the memory capacity can be increased.
For example, when the minimum size of design rule is defined as “F”, the size of a memory cell formed from a select MOS transistor and TMR element is 8F2. However, a memory cell including only a TMR element is 4F2. That is, the memory cell including only a TMR element can realize a cell size about ½ that of the memory cell formed from a select MOS transistor and TMR element.
However, in the cross-point cell array structure, since no select MOS transistor is present, a problem is posed in read operation.
In the cross-point cell array structure, a read current is supplied between the selected word line and the selected bit line. When the read current flows to the TMR element at the intersection between the selected word line and the selected bit line, the voltage drop amount of the selected TMR element is detected.
For example, as a known read method, the voltage applied across the selected TMR element is measured by 4-terminal resistance measurement and compared with a reference potential, thereby discriminating read data. As another known read method, one terminal of the selected TMR element is connected to one of two input terminals of an operational amplifier, and the output potential of the operational amplifier is compared with a reference potential, thereby discriminating read data.
In the latter read method using an operational amplifier, a ground potential is applied to the other input terminal of the operational amplifier. In addition, a resistive element is connected between the output terminal and one input terminal of the operational amplifier.
Let Rm be the resistance value of the TMR element, Ro be the resistance value of the resistive element connected between the output terminal and one input terminal of the operational amplifier, and Vm be the voltage applied across the TMR element. Since an output potential Vo of the operational amplifier is given byVm/Rm=−Vo/RoVo=−Vm×(Ro/Rm)  (1)
As is apparent from equation (1), in the read method using an operational amplifier, when Ro is sufficiently larger than Rm, a large gain can be obtained.
In either of the two read methods described above, a read current flows between the selected word line and the selected bit line.
In the cross-point cell array structure, however, since no select MOS transistor is connected to the TMR element, the read current flows through various paths via not only the selected TMR element but also other unselected TMR elements. For this reason, it is difficult to accurately evaluate the resistance value of only the selected TMR element (or the voltage applied across the TMR element).
For example, consider a magnetic random access memory having a cross-point cell array structure as shown in FIGS. 53 and 54.
In the read operation, for example, when an output signal RSL3 from a row decoder RD3 and an output signal CSL3 from a column decoder CD3 change to “H”, a row select switch RSW3 and column select switch CSW3 are turned on.
As a result, in FIG. 53, the read current flows from a constant current source I1 to an operational amplifier OP1 through a word line WL3 and bit line BL3.
At this time, output signals RSL1, RSL2, RSL4, and RSL5 from row decoders RD1, RD2, RD4, and RD5 are “L”. Output signals CSL1, CSL2, CSL4, and CSL5 from column decoders CD1, CD2, CD4, and CD5 are also “L”.
Hence, unselected word lines WL1, WL2, WL4, and WL5 and unselected bit lines BL1, BL2, BL4, and BL5 are in a floating state.
That is, TMR elements connected to the unselected word lines WL1, WL2, WL4, and WL5 are short-circuited to each other at one terminal. The other terminal of each TMR element connected to a corresponding one of the unselected bit lines BL1, BL2, BL4, and BL5 is also short-circuited.
For this reason, as an equivalent circuit of the cross-point cell array structure in the read operation, unselected TMR elements are complexly connected in series or in parallel to a selected TMR element MTJ33. This means a decrease in read signal amount of the selected TMR element MTJ33. Consequently, it is difficult to accurately evaluate the resistance value of only the selected TMR element MTJ33 by a sense amplifier S/A.
Referring to FIG. 54, in the read operation, when the output signal RSL3 from the row decoder RD3 and the output signal CSL3 from the column decoder CD3 change to “H”, the row select switch RSW3 and column select switch CSW3 are turned on. In addition, since signals bCSL1, bCSL2, bCSL4, and bCSL5 change to “H”, transistors BSW1, BSW2, BSW4, and BSW5 are turned on.
As a result, the read current flows from the constant current source I1 to the operational amplifier OP1 through the word line WL3 and bit line BL3. In addition, the current flowing to the selected bit line BL3 flows toward a ground point VSS because of the input scheme of the operational amplifier OP1. Simultaneously, the read current flows toward the ground point VSS through the unselected bit lines BL1, BL2, BL4, and BL5.
The amount of the current that flows to the operational amplifier OP1 through the selected bit line BL3 is very small due to the influence of the current that flows through the unselected bit lines BL1, BL2, BL4, and BL5. Especially, at the start of read operation, the signal current does not flow to the operational amplifier OP1 at all, resulting in a delay in read operation.
The current that flows to the selected bit line BL3 also finally flows to the ground point VSS because of the input scheme of the operational amplifier OP1. When the unselected bit lines BL1, BL2, BL4, and BL5 in the parallelly connected state have low resistances, including the parasitic resistances, the necessary signal current does not flow to the operational amplifier OP1 even after the elapse of a sufficient time.
In FIGS. 53 and 54, in the paths from the selected word line WL3 to the selected bit line BL3, the primary path that passes through the selected TMR element MTJ33 and typical examples of other paths are indicated by arrows.